The escalating requirements for increased densification and performance in ultra-large scale integration semiconductor wiring require integrated circuits capable of operating at higher speeds while having reduced-size geometries and greater packing densities. As geometries shrink into the sub-micron range, channel lengths are reduced, thereby exacerbating the impact of hot-carrier effects with a consequential degradation in CMOS performance.
It is recognized that source side parasitic resistance induces a serious decrease in the drain current of a MOSFET. Explanations include a decrease in the effective gate voltage from the self-biased negative feedback. See Horiuchi et al., "An Asymmetric Sidewall Process of High Performance LDD MOSFET's, " IEEE Transactions on Electron Devices, Vol. 41, No. 2, February 1994, pp. 186-190. Horiuchi et al. report that the drain current is not significantly effected by the drain side parasitic resistance when the MOSFET is operated in the saturation region. Several prior art attempts to address the source parasitic resistance problem include the formation of a double-diffused drain and a lightly doped drain (LDD) or a moderately doped drain (MDD).
As used throughout the present disclosure, LDD denotes a conventional lightly doped source/drain implant, typically having an impurity concentration of about 2.times.10.sup.18 to about 5.times.10.sup.18 atoms/cm.sup.3. As used throughout the present disclosure, the expression MDD denotes a conventional moderately doped source/drain implant, typically having an impurity concentration of about 5.times.10.sup.18 to about 2.times.10.sup.19 atoms/cm.sup.3. As also used throughout this application, HDD denotes a conventional heavily doped source/drain implant, typically having an impurity concentration of about 2.times.10.sup.19 to about 2.times.10.sup.20 atoms/cm.sup.3.
A conventional LDD/MDD transistor structure is illustrated in FIG. 1 and comprises substrate 10 having an active region isolated by surrounding field oxide region 11. The active region includes a MOSFET comprising source/drain regions 12, 13, and gate electrode 14 spaced apart from semiconductor substrate 10 by gate insulating layer 15. Sidewall spacers 16 are formed on side surfaces of gate electrode 14 serving to mask portions of the LDD/MDD implants during HDD implantations. Source/drain regions 12, 13 are characterized by LDD/MDD regions 17A and HDD regions 17B. The LDD/MDD implanted junction is designated by reference numeral 18, while the source/drain implant junction is designated by reference numeral 19.
The requirement for reduced geometries necessities reduced channel lengths and gate insulating layers having reduced thicknesses. The conventional LDD/MDD transistor structure depicted in FIG. 1, consequently, becomes less effective in remedying performance degradation, particularly due to the increased parasitic resistance of the source and consequential decreased drain current. Moreover, conventional techniques for forming a typical LDD/MDD type of transistor structure depicted in FIG. 1 are complex and generates additional performance problems. Accordingly, efforts have been made to provide an asymmetrically doped source/drain transistor structure.
A conventional asymmetrically doped source/drain MOSFET structure is depicted in FIG. 2 and comprises semiconductor substrate 20 having an active region isolated by surrounding field oxide region 21. The active region includes a MOSFET comprising drain region 22, source region 23, and gate electrode 24 spaced apart from semiconductor substrate 20 by gate insulating layer 25. Sidewall spacers 26 are selectively formed on the side surfaces of gate electrode 24, and comprise a conventional sidewall spacer insulating material, such as silicon dioxide or polycrystalline silicon. The MOSFET structure of FIG. 2 differs from that of FIG. 1, in that source region 23 does not contain LDD/MDD region 27 as formed in drain region 22; whereas, both the source 12 and drain 13 regions of the FIG. 1 MOSFET comprise LDD/MDD implants 17A. Thus, a conventional asymmetric source/drain structure comprises an LDD/MDD junction formed only in the drain region. In this way, the source side resistance and the voltage across the gate electrode to the source junction are reduced, thereby improving the saturation drive current and transistor reliability, particularly hot-carrier injection.
A conventional method of forming an asymmetric source/drain structure, such as that depicted in FIG. 2, comprises photoresistive masking and selectively forming sidewall spacers, as disclosed by Horiuchi et al. For example, sequential stages of a conventional method for forming an asymmetrical source/drain transistor are depicted in FIGS. 3 and 4. Adverting to FIG. 3, gate electrode 31 is formed on semiconductor substrate 30 with gate insulating layer 32 therebetween. A conventional LDD/MDD impurity implantation is conducted using gate electrode 31 as a mask to form LDD/MDD source/drain implants 33. A conventional LDD impurity implantation is typically conducted at an implantation energy of about 20 Kev to about 40 Kev to form an LDD implant having an impurity concentration of about 2.times.10.sup.18 to about 5.times.10.sup.18 atoms/cm.sup.3. A conventional MDD impurity implantation is typically conducted at an implantation energy of about 10 Kev to about 20 Kev to form an MDD implant having an impurity concentration of about 5.times.10.sup.18 to about 2.times.10.sup.19 atoms/cm.sup.3.
An asymmetric photoresist mask 34 is formed covering drain region D. An HDD impurity implantation, indicated by arrows 36, is conducted to form an HDD source implant 35. A conventional HDD impurity implantation is typically conducted at an implantation energy of about 1 Kev to about 10 Kev to form an HDD implant having an impurity concentration of about 2.times.10.sup.+19 to about 2.times.10.sup.+20 atoms/cm.sup.3.
Asymmetric photoresist mask 34 is then removed, and sidewall spacers 40 are formed on the side surfaces of gate electrode 31, as illustrated in FIG. 4. With continued reference to FIG. 4, a second HDD impurity implantation, indicated by arrows 41, is conducted to form HDD source/drain implants 42, thereby forming the basic asymmetrically doped source/drain regions of the MOSFET. Thermal treatment is conventionally conducted after the implantations or during subsequent processing to complete and activate the source/drain regions.
The conventional procedure illustrated in FIGS. 3 and 4 is problematic, particularly for deep sub-micron transistor generations, wherein a thin gate dielectric is employed, typically about 15 .ANG. to about 200 .ANG.. Such problems stem, in part, from the penetration of impurities during the HDD implantations into gate electrode 31, illustrated by impurity atoms 37 in FIG. 3, and impurity atoms 37 and 43 in FIG. 4. As a result, a portion of the gate electrode receives an excessive impurity dosage which, in turn, causes penetration through increasingly thinner gate insulating layers and into semiconductor substrate 30, as into a portion of the channel region designated by reference numeral X in FIG. 4. Such penetration of the semiconductor substrate in the channel region deteriorates transistor performance and characteristics, as by causing a shift in the threshold voltage. As a practical matter, perfect alignment of the photoresist and the side surface of the gate electrode (FIG. 3) cannot be achieved. Accordingly, due to the requisite misalignment tolerance for shielding drain region D during the initial HDD source implantation, impurity penetration into a portion of the channel region of the semiconductor substrate is exacerbated.
Accordingly, there is a need for semiconductor methodology to form asymmetrically doped source/drain regions of an MOSFET, wherein impurity penetration of the gate insulating layer into the channel region of the semiconductor substrate is prevented. There further exists a need for simplified, deep sub-micron semiconductor methodology, wherein the resulting transistor comprises an asymmetrically doped source/drain region exhibiting an increased operating speed, improved reliability and an improved signal-to-noise ratio.